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[VHDL-FPGA-Verilog] 用FPGA实现DDS信号发生及用MODELSIM仿真

Description: 该工程是用verilog编写，FPGA内部产生ROM及ADD加法器。ROM中存正弦波信号。文件夹中还包含modelsim仿真。
Platform: | Size: 2527046 | Author: zhengguo22 | Hits:

[Windows Develop] ram

Description: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
Platform: | Size: 1024 | Author: 杨艳 | Hits:

[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

Description: 用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures
Platform: | Size: 68608 | Author: 阿乐 | Hits:

[Embeded-SCM Develop] DDSsignalgen

Description: dds信号发生器-dds signal generator ask, am, fskdds signal generator ask, am, fskdds signal generator ask, am, fskdds signal generator ask, am, FSK
Platform: | Size: 3331072 | Author: appolo | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[Software Engineering] ddsbyvhdl

Description: 摘要：介绍了基于可编程逻辑器件CPLD和直接数字频率合成技术（DDS）的三相多波形函数发生器的基本原理，并在此基础上给出了基于CPLD的各模块设计方法及其VHDL源程序-Abstract : Based on the CPLD and direct digital frequency synthesis (DDS) of a three-phase multi-function waveform Generator to the basic principles and on this basis given the CPLD based on the module design and VHDL source
Platform: | Size: 47104 | Author: 陈鑫 | Hits:

[VHDL-FPGA-Verilog] key

Description: 一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
Platform: | Size: 199680 | Author: 林虎 | Hits:

[VHDL-FPGA-Verilog] DDS1

Description: DDS信号发生器，能产生多种波形，正玄波，三角波，方波，频率可调，相位可调-DDS signal generator, can produce a variety of waveforms, are mysterious wave, triangle wave, square wave, frequency tunable, phase adjustable
Platform: | Size: 1108992 | Author: 张俊 | Hits:

[VHDL-FPGA-Verilog] AD9851

Description: 用VHDL语言编写的DDS正弦函数发生器-Using VHDL language DDS sine function generator
Platform: | Size: 500736 | Author: cfsword | Hits:

[VHDL-FPGA-Verilog] AD9852

Description: 数字频率合成器芯片AD9852 的配置文件，HDL级的Verilog代码-DDS chip AD9852 profile, HDL-level Verilog code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[Special Effects] yuv2rgb

Description:
Platform: | Size: 1024 | Author: scounix | Hits:

[VHDL-FPGA-Verilog] veriloghdl

Description: 来自精益求精的德国人讲授的VERILOG课件，想接触FPGA/CPLD开发的人是必看的课件。
Platform: | Size: 4944896 | Author: 王方 | Hits:

[VHDL-FPGA-Verilog] sine

Description: Verilog编程，利用FPGA实现两路正弦波的信号输出，也可以扩展成六路正弦输出-Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Platform: | Size: 4792320 | Author: 陈剑 | Hits:

[VHDL-FPGA-Verilog] CORDIC_DDS_16bit

Description: dds频率生成文件，看看有没有人喜欢认真阅读您的文件包然后写出其具-dds frequency generated files, see if there is no one really wants to read your document carefully and then write its packet with
Platform: | Size: 1357824 | Author: zhangxi | Hits:

[VHDL-FPGA-Verilog] 0522

Description: 自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波.-Their own design this year
Platform: | Size: 1375232 | Author: dawn | Hits:

[Other Embeded program] dds_drive.c

Description: DDS发生器NIOS .c文件,在NIOSII中可以配合Verilog代码生成的自定义外设产生DDS信号-DDS generator NIOS. C files, NIOSII can be in Verilog code generation with custom peripherals DDS generated signal
Platform: | Size: 4096 | Author: 白天 | Hits:

[Software Engineering] dds

Description: 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
Platform: | Size: 1695744 | Author: 姜兆刚 | Hits:

[SCM] sgs32

Description: Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable duty cycle. See readme.doc. Here only provide a source module that contains the top-level sub-modules sgs32.v settings dds.v and pll module altp.v and waveform-driven document
Platform: | Size: 59392 | Author: TTHR | Hits:

[VHDL-FPGA-Verilog] accumulator

Description: 实现累加器的verilog源码，广泛应用在通信电路设计中-The realization of accumulator Verilog source, widely used in communication circuit design
Platform: | Size: 1024 | Author: 文明 | Hits:
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